kessetsuOpen Web Hub

Executable circuit engineering

Circuit engineering you can execute.

Design circuits in the browser or give an AI agent measurable requirements. Kessetsu compiles, simulates, verifies, and exports every iteration through the same engineering core.

Open Web Hub Install the CLI
No account required Real SPICE simulation Local browser runtime
agent-loop.kess
RECORDED CORRECTION EXAMPLE · GENERIC MODELS

Four-stage amplifier · 8 Ω load · ≈2 W output · gain ≈55 · device dissipation <2 W

$ kess test - --format json
iteration 01  FAIL  output_power = 997.7 mW
agent revision  load 16 Ω → 8 Ω
iteration 02  PASS  output_power = 1.995 W
12 / 12 requirements passedkessetsu.cli.v1

Agent workflow

Give your agent requirements, not blind trust.

A capable agent designs and revises the circuit. Kessetsu gives it deterministic engineering feedback at every step.

  1. 01Specify

    Describe topology constraints, load, gain, power, stress, or another supported measurable requirement.

  2. 02Design

    The agent writes a complete `.kess` circuit and calls the CLI directly through stdin.

  3. 03Verify and revise

    Structured diagnostics and assertion results expose exactly what failed, without scraping terminal prose.

  4. 04Continue anywhere

    Keep the verified source or export the schematic, SPICE netlist, KiCad, and LTspice artifacts.

Kessetsu is AI-provider independent. Your agent uses a versioned CLI contract; the circuit engine stays the same.

Prefer to work directly?

The complete workflow, in your browser.

Edit source, inspect a professional schematic, run real OP/transient/AC/DC simulation, evaluate requirements, and download engineering artifacts without an account or installation.

  • The same canonical Rust Core as the CLI
  • Connectivity-verified automatic schematics
  • Interactive results and explicit PASS/FAIL assertions

Work with analog circuits, reusable stages and local device models. Follow the circuit tutorial.

kessetsuConnectivity verified
Source
net GND
net IN
net OUT
source VIN ac(1V)
resistor R1 1k
capacitor C1 159.154943nF
connect VIN.minus to GND
connect VIN.plus to IN
connect R1.p1 to IN
connect R1.p2 to OUT
connect C1.p1 to OUT
connect C1.p2 to GND
simulate ac dec 40 10Hz 100kHz
assert gain(V(OUT),V(IN)) > 0.99
assert cutoff(V(OUT),V(IN)) > 990Hz
assert cutoff(V(OUT),V(IN)) < 1010Hz
assert phase(V(OUT),V(IN),1kHz) > -46deg
assert phase(V(OUT),V(IN),1kHz) < -44deg
Schematic
C1159 nFR11 kΩVINAC 1 V
Simulation
5 / 5 requirements passedcutoff = 1.000 kHz
One source. One Core. The same verified result in Web and CLI.

Circuit tools

Start with a calculation. Keep the circuit.

Choose nominal component values, see the achieved result and open an editable circuit for simulation and export.

Loaded voltage divider Size resistors for an actual load. Inspect output voltage, current and dissipation.RC low-pass filter Set a cutoff, choose standard R/C values and inspect the frequency response in the editor.

Shared engineering core

Verify once. Continue anywhere.

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Kessetsu CoreCompile · ERC · SPICE · Assert · Layout
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AI agentCLI + JSON
SVGPNGPDFSchematic JSONSPICEKiCadLTspice